We acknowledge and respect the Lək̓ʷəŋən (Songhees and Xʷsepsəm/Esquimalt) Peoples on whose territory the university stands, and the Lək̓ʷəŋən and W̱SÁNEĆ Peoples whose historical relationships with the land continue to this day.
CRN(s): | Section A01 CRN: 20915 | |||
Term: | 2025 | |||
Course Start: | 2025-01-06 | |||
Course End: | 2025-04-25 | |||
Withdrawal with 100% reduction of tuition fees: | 2025-01-19 | |||
Withdrawal with 50% reduction of tuition fees: | 2025-02-09 | |||
Last day for withdrawal (no fees returned): | 2025-02-28 |
Section: | Location: | Classes Start: | Classes End: | Days of week: | Hours of day: | Instructor: |
A01 | ELL 062 | 2025-01-06 | 2025-04-04 | MR | 13:00-14:20 | David Capson |
B01 | ELW A359 | 2025-01-21 | 2025-01-21 | T | 15:00-17:50 | |
B01 | ELW A359 | 2025-01-28 | 2025-01-28 | T | 15:00-17:50 | |
B01 | ELW A359 | 2025-02-11 | 2025-02-11 | T | 15:00-17:50 | |
B01 | ELW A359 | 2025-03-04 | 2025-03-04 | T | 15:00-17:50 | |
B01 | ELW A359 | 2025-03-18 | 2025-03-18 | T | 15:00-17:50 | |
B02 | ELW A359 | 2025-01-21 | 2025-01-21 | T | 15:00-17:50 | |
B02 | ELW A359 | 2025-02-04 | 2025-02-04 | T | 15:00-17:50 | |
B02 | ELW A359 | 2025-02-25 | 2025-02-25 | T | 15:00-17:50 | |
B02 | ELW A359 | 2025-03-11 | 2025-03-11 | T | 15:00-17:50 | |
B02 | ELW A359 | 2025-03-25 | 2025-03-25 | T | 15:00-17:50 | |
B03 | ELW A359 | 2025-01-22 | 2025-01-22 | W | 14:30-17:20 | |
B03 | ELW A359 | 2025-01-29 | 2025-01-29 | W | 14:30-17:20 | |
B03 | ELW A359 | 2025-02-12 | 2025-02-12 | W | 14:30-17:20 | |
B03 | ELW A359 | 2025-03-05 | 2025-03-05 | W | 14:30-17:20 | |
B03 | ELW A359 | 2025-03-19 | 2025-03-19 | W | 14:30-17:20 |
Name: David Capson
Office: EOW 419
Phone: (250) 721-6030
Email: capson at uvic dot ca
Office Hours: TBD
Prerequisites
TA names and email contact information will be provided via the course Brightspace page
To learn advanced concepts in combinational and sequential logic circuit design, analysis, implementation, and verification. To gain experience with the use of VLSI design methodologies based on hardware description language concepts and coding practices. To acquire experience in the use of electronic design automation software tools. To learn fundamental strategies in VLSI systems testing and verification.
Understanding advanced combinational and sequential logic design concepts including examples of CMOS logic, high performance arithmetic structures, memory systems, and FPGA architectures. Learning how to optimize and analyze timing and synchronization of finite state machines. Gaining experience in a hardware description language (e.g. VHDL) for structural, behavioural and RTL design. Learning how to use development and simulation tools with a modern EDA software tool suite. Acquiring an understanding of fundamentals in VLSI testing including fault models, design for test, automatic test pattern generation, and signature analysis. Understanding concepts in systems design using soft processors and IP blocks.
High performance arithmetic circuit design and analysis (addition, multiplication). CMOS logic for VLSI systems. FPGA architectures and on-chip resources. Optimization of finite state machines (FSM), ASMs, timing methodologies and synchronization. Design and application of Linear Feedback Shift Registers (LFSR). Clock domains, hazards, and metastability. Static Timing Analysis (STA). Memory architecture and systems, error detection & correction. Hardware Description Language (e.g.VHDL), structural, behavioural and RTL design, simulation, testbenches, coding styles, CAD tools, FPGA implementation. Soft processors for FPGA, synthesizable sytem bus design and IP block-based design. Design examples of high speed interfaces (e.g. video, serial protocols). Design for high speed using pipelining and re-timing. VLSI testing concepts and fault models, design for test, automatic test pattern generation and signature analysis.
Required Text | Required Text | ||
---|---|---|---|
Title: | Handbook of Digital CMOS Technology, Circuits, and Systems | Title: | RTL Hardware Design using VHDL |
Author: | K. Abbas | Author: | P. Chu |
Publisher/Year: | Springer/2020 available via UVic library | Publisher/Year: | Wiley/2006 available via UVic library |
Reference Materials | |||
Title: | Microelectronic Circuits, 8th edition | ||
Author: | Sedra and Smith | ||
Publisher/Year: | Oxford University Press, 2020 |
Recomended tools:
In this course, the use of generative AI is welcomed to assist in completing assignments and lab reports. Therefore, you are authorized to use generative AI tools such as ChatGPT. Also note that you can opt for not using generative AI at all to complete course assignments/lab reports successfully.
In the case you opt to use generative AI, you must provide proper citation of the tools you used, clearly identify any and all content that is AI generated (including software and HDL code), and describe how you used it (for initial research, preparing outline, editing, etc).
It is important to note that you are responsible for a detailed understanding of the entire content of ALL assignments and lab reports (including software and HDL code) that you submit, even when using generative AI. Assignments and labs are designed to encompass examinable materials that may feature in any of the Tests.
Although the course allows the use of generative AI, please be aware of the following flaws when using the tools:
Assessment Tool | Weight | Date |
---|---|---|
4 Labs (10% each) | 40% | TBD |
3 Assignments (5% each) | 15% | TBD |
Test #1 | 15% | TBD |
Test #2 | 15% | TBD |
Test #3 | 15% | TBD |
There will be no final exam.
Consructive feedback from students to the instructor is encouraged and welcomed at any time during the course. Feedback can be via email or in-person during office hours.
Note to students: Students who have issues with the conduct of the course should discuss them with the instructor first. If these discussions do not resolve the issue, then students should feel free to contact the Chair of the Department by email, or the Chair's Assistant to set up an appointment.
Course Lecture Notes: Unless otherwise noted, all course materials supplied to students in this course have been prepared by the instructor and are intended for use in this course only. These materials are NOT to be re-circulated digitally, whether by email or by uploading or copying to websites, or to others not enrolled in this course. Violation of this policy may in some cases constitute a breach of academic integrity as defined in the UVic Calendar.
Equality: This course aims to provide equal opportunities and access for all students to enjoy the benefits and privileges of the class and its curriculum and to meet the syllabus requirements. Reasonable and appropriate accommodation will be made available to students with documented disabilities (physical, mental, learning) in order to give them the opportunity to successfully meet the essential requirements of the course. The accommodation will not alter academic standards or learning outcomes, although the student may be allowed to demonstrate knowledge and skills in a different way. It is not necessary for you to reveal your disability and/or confidential medical information to the course instructor. If you believe that you may require accommodation, the course instructor can provide you with information about confidential resources on campus that can assist you in arranging for appropriate accommodation. Alternatively, you may want to contact the Centre for Accessible Learning. The University of Victoria is committed to promoting, providing, and protecting a positive, and supportive and safe learning and working environment for all its members.
Academic Integrity requires commitment to the values of honesty, trust, fairness, respect, and responsibility. It is expected that students, faculty members and staff at the University of Victoria, as members of an intellectual community, will adhere to these ethical values in all activities related to learning, teaching, research and service. Any action that contravenes this standard, including misrepresentation, falsification or deception, undermines the intention and worth of scholarly work and violates the fundamental academic rights of members of our community. This policy is designed to ensure that the university’s standards are upheld in a fair and transparent fashion.
Attendance: Students are expected to attend all classes in which they are enrolled. An academic unit may require a student to withdraw from a course if the student is registered in another course that occurs at the same time.
An Instructor may refuse a student admission to a lecture, laboratory, online course discussion or learning activity, tutorial or other learning activity set out in the course outline because of lateness, misconduct, inattention or failure to meet the responsibilities of the course set out in the course outline. Students who neglect their academic work may be assigned a final grade of N or debarred from final examinations.
Students who do not attend classes must not assume that they have been dropped from the course by an academic unit or an instructor. Courses that are not formally dropped will be given a failing grade, students may be required to withdraw and will be required to pay the tuition fee for the course.